Retrograde well structure for a CMOS imager

ABSTRACT

A retrograde and periphery well structure for a CMOS imager is disclosed which improves the quantum efficiency and signal-to-noise ratio of the photosensing portion imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. The periphery well contains peripheral logic circuitry for the imager. By providing retrograde and peripheral wells, circuitry in each can be optimized. Also disclosed are methods for forming the retrograde and peripheral well.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. applicationSer. No. 09/334,261 filed Jun. 16, 1999 (attorney docket numberM4065.0107), entitled “Retrograde Well Structure For A CMOS Imager” thedisclosure of which is incorporated by reference herein.

FIELD OF THE INVENTION

[0002] The present invention relates generally to improved semiconductorimaging devices and in particular to a silicon imaging device that canbe fabricated using a standard CMOS process.

BACKGROUND OF THE INVENTION

[0003] There are a number of different types of semiconductor-basedimagers, including charge coupled devices (CCDs), photodiode arrays,charge injection devices and hybrid focal plane arrays. CCD technologyis often employed for image acquisition and enjoys a number ofadvantages which makes it the incumbent technology, particularly forsmall size imaging applications. CCDs are capable of large formats withsmall pixel size and they employ low noise charge domain processingtechniques.

[0004] However, CCD imagers also suffer from a number of disadvantages.For example, they are susceptible to radiation damage, they exhibitdestructive read-out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there have been some attempts to integrate on-chipsignal processing with CCD arrays, these attempts have not been entirelysuccessful. CCDs also must transfer an image by line charge transfersfrom pixel to pixel, requiring that the entire array be read out into amemory before individual pixels or groups of pixels can be accessed andprocessed. This takes time. CCDs may also suffer from incomplete chargetransfer from pixel to pixel which results in image smear.

[0005] Because of the inherent limitations in CCD technology, there isan interest in CMOS imagers for possible use as low cost imagingdevices. A fully compatible CMOS sensor technology enabling a higherlevel of integration of an image array with associated processingcircuits would be beneficial to many digital applications such as, forexample, in cameras, scanners, machine vision systems, vehiclenavigation systems, video telephones, computer input devices,surveillance systems, auto focus systems, star trackers, motiondetection systems, image stabilization systems and data compressionsystems for high-definition television.

[0006] The advantages of CMOS imagers over CCD imagers are that CMOSimagers have a low voltage operation and low power consumption; CMOSimagers are compatible with integrated on-chip electronics (controllogic and timing, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD because standard CMOS processing techniques can beused. Additionally, low power consumption is achieved for CMOS imagersbecause only one row of pixels at a time needs to be active during thereadout and there is no charge transfer (and associated switching) frompixel to pixel during image acquisition. On-chip integration ofelectronics is particularly advantageous because of the potential toperform many signal conditioning functions in the digital domain (versusanalog signal processing) as well as to achieve a reduction in systemsize and cost.

[0007] A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photogate,photoconductor or a photodiode overlying a substrate for accumulatingphoto-generated charge in the underlying portion of the substrate. Areadout circuit is connected to each pixel cell and includes at least anoutput field effect transistor formed in the substrate and a chargetransfer section formed on the substrate adjacent the photogate,photoconductor or photodiode having a sensing node, typically a floatingdiffusion node, connected to the gate of an output transistor. Theimager may include at least one electronic device such as a transistorfor transferring charge from the underlying portion of the substrate tothe floating diffusion node and one device, also typically a transistor,for resetting the node to a predetermined charge level prior to chargetransference.

[0008] In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate. For photodiodes, image lag can beeliminated by completely depleting the photodiode upon readout.

[0009] CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12), pp.2046-2050 (1996); Mendis et al., “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453(1994), as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

[0010] To provide context for the invention, an exemplary CMOS imagingcircuit is described below with reference to FIG. 1. The circuitdescribed below, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

[0011] Reference is now made to FIG. 1 which shows a simplified circuitfor a pixel of an exemplary CMOS imager using a photogate and having apixel photodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

[0012] The photodetector circuit 14 is shown in part as across-sectional view of a semiconductor substrate 16 typically a p-typesilicon, having a surface well of p-type material 20. An optional layer18 of p-type material may be used if desired, but is not required.Substrate 16 may be formed of, for example, Si, SiGe, Ge, or GaAs.Typically the entire substrate 16 is p-type doped silicon substrate andmay contain a surface p-well 20 (with layer 18 omitted), but many otheroptions are possible, such as, for example p on p− substrates, p on p+substrates, p-wells in n-type substrates or the like. The terms wafer orsubstrate used in the description includes any semiconductor-basedstructure having an exposed surface in which to form the circuitstructure used in the invention. Wafer and substrate are to beunderstood as including silicon-on-insulator (SOI) technology,silicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a wafer or substrate in the following description,previous process steps may have been utilized to form regions/junctionsin the base semiconductor structure or foundation.

[0013] An insulating layer 22 such as, for example, silicon dioxide isformed on the upper surface of p-well 20. The p-type layer may be ap-well formed in substrate 16. A photogate 24 thin enough to passradiant energy or of a material which passes radiant energy is formed onthe insulating layer 22. The photogate 24 receives an applied controlsignal PG which causes the initial accumulation of pixel charges in n+region 26. The n+ type region 26, adjacent one side of photogate 24, isformed in the upper surface of p-well 20. A transfer gate 28 is formedon insulating layer 22 between n+ type region 26 and a second n+ typeregion 30 M formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulatedthereat to the gate of a source follower transistor 36 described below.

[0014] A reset gate 32 is also formed on insulating layer 22 adjacentand between n+ type region 30 and another n+ region 34 which is alsoformed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form areset transistor 31 which is controlled by a reset signal RST. The n+type region 34 is coupled to voltage source V_(DD), e.g., 5 volts. Thetransfer and reset transistors 29, 31 are n-channel transistors asdescribed in this implementation of a CMOS imager circuit in a p-well.It should be understood that it is possible to implement a CMOS imagerin an n-well in which case each of the transistors would be p-channeltransistors. It should also be noted that while FIG. 1 shows the use ofa transfer gate 28 and associated transistor 29, this structure providesadvantages, but is not required.

[0015] Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage sourceV_(DD) and the drain of transistor 38 coupled to a lead 42. The drain ofrow select transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source V_(SS), e.g. 0 volts. Transistor 39 is kept on by asignal V_(LN) applied to its gate.

[0016] The imager includes a readout circuit 60 which includes a signalsample and hold (S/H) circuit including a S/H n-channel field effecttransistor 62 and a signal storage capacitor 64 connected to the sourcefollower transistor 36 through row transistor 38. The other side of thecapacitor 64 is connected to a source voltage V_(SS). The upper side ofthe capacitor 64 is also connected to the gate of a p-channel outputtransistor 66. The drain of the output transistor 66 is connectedthrough a column select transistor 68 to a signal sample output nodeV_(OUTS) and through a load transistor 70 to the voltage supply V_(DD).A signal called “signal sample and hold” (SHS) briefly turns on the S/Htransistor 62 after the charge accumulated beneath the photogateelectrode 24 has been transferred to the floating diffusion node 30 andfrom there to the source follower transistor 36 and through row selecttransistor 38 to line 42, so that the capacitor 64 stores a voltagerepresenting the amount of charge previously accumulated beneath thephotogate electrode 24.

[0017] The readout circuit 60 also includes a reset sample and hold(S/H) circuit including a S/H transistor 72 and a signal storagecapacitor 74 connected through the S/H transistor 72 and through the rowselect transistor 38 to the source of the source follower transistor 36.The other side of the capacitor 74 is connected to the source voltageV_(SS). The upper side of the capacitor 74 is also connected to the gateof a p-channel output transistor 76. The drain of the output transistor76 is connected through a p-channel column select transistor 78 to areset sample output node V_(OUTR a)nd through a load transistor 80 tothe supply voltage V_(DD). A signal called “reset sample and hold” (SHR)briefly turns on the S/H transistor 72 immediately after the resetsignal RST has caused reset transistor 31 to turn on and reset thepotential of the floating diffusion node 30, so that the capacitor 74stores the voltage to which the floating diffusion node 30 has beenreset.

[0018] The readout circuit 60 provides correlated sampling of thepotential of the floating diffusion node 30, first of the reset chargeapplied to node 30 by reset transistor 31 and then of the stored chargefrom the photogate 24. The two samplings of the diffusion node 30charges produce respective output voltages V_(OUTR) and V_(OUTS) of thereadout circuit 60. These voltages are then subtracted(V_(OUTS)−V_(OUTD)) by subtractor 82 to provide an output signalterminal 81 which is an image signal independent of pixel to pixelvariations caused by fabrication variations in the reset voltagetransistor 31 which might cause pixel to pixel variations in the outputsignal.

[0019]FIG. 2 illustrates a block diagram for a CMOS imager having apixel array 200 with each pixel cell being constructed in the mannershown by element 14 of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array200. Pixel array 200 comprises a plurality of pixels arranged in apredetermined number of columns and rows. The pixels of each row inarray 200 are all turned on at the same time by a row select line, e.g.,line 86, and the pixels of each column are selectively output by acolumn select line, e.g., line 42. A plurality of rows and column linesare provided for the entire array 200. The row lines are selectivelyactivated by the row driver 210 in response to row address decoder 220and the column select lines are selectively activated by the columndriver 260 in response to column address decoder 270. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 250 which controls address decoders 220, 270 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 210, 260 which apply driving voltage tothe drive transistors of the selected row and column lines.

[0020]FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and pulsed from5V to 0V during integration. The reset signal RST is nominally set at2.5V. As can be seen from the figure, the process is begun at time t₀ bybriefly pulsing reset voltage RST to 5V. The RST voltage, which isapplied to the gate 32 of reset transistor 31, causes transistor 31 toturn on and the floating diffusion node 30 to charge to the V_(DD)voltage present at n+ region 34 (less the voltage drop V_(TH) oftransistor 31). This resets the floating diffusion node 30 to apredetermined voltage (V_(DD)−V_(TH)). The charge on floating diffusionnode 30 is applied to the gate of the source follower transistor 36 tocontrol the current passing through transistor 38, which has been turnedon by a row select (ROW) signal, and load transistor 39. This current istranslated into a voltage on line 42 which is next sampled by providinga SHR signal to the S/H transistor 72 which charges capacitor 74 withthe source follower transistor output voltage on line 42 representingthe reset charge present at floating diffusion node 30. The PG signal isnext pulsed to 0 volts, causing charge to be collected in n+ region 26.

[0021] A transfer gate voltage TX, similar to the reset pulse RST, isthen applied to transfer gate 28 of transistor 29 to cause the charge inn+ region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81. It should also be notedthat CMOS imagers may dispense with the transfer gate 28 and associatedtransistor 29, or retain these structures while biasing the transfertransistor 29 to an always “on” state.

[0022] The operation of the charge collection of the CMOS imager isknown in the art and is described in several publications such as Mendiset al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172,pp. 19-29 (1994); Mendis et al., “CMOS Active Pixel Image Sensors forHighly Integrated Imaging Systems,” IEEE Journal of Solid StateCircuits, Vol. 32(2) (1997); and Eric R. Fossum, “CMOS Image Sensors:Electronic Camera on a Chip,” IEDM Vol. 95, pp. 17-25 (1995) as well asother publications. These references are incorporated herein byreference.

[0023] Quantum efficiency is a problem in some imager applications dueto the diffusion of signal carriers out of the photosite and into thesubstrate, where they become effectively lost. The loss of signalcarriers results in decreased signal strength, increased cross talk, andthe reading of an improper value for the adjacent pixels.

[0024] There is needed, therefore, an improved pixel sensor cell for usein an imager that exhibits improved quantum efficiency, a bettersignal-to-noise ratio, and reduced cross talk. A method of fabricating apixel sensor cell exhibiting these improvements is also needed.

SUMMARY OF THE INVENTION

[0025] The present invention provides a pixel sensor cell formed in aretrograde well in a semiconductor substrate having improved quantumefficiency, an improved signal-to-noise ratio, and reduced cross talk.The retrograde well comprises a doped region with a vertically gradeddopant concentration that is lowest at or near the substrate surface,and highest at the bottom of the well. The retrograde well would have anentire array of pixels formed therein, and may also have peripheralcircuitry formed therein. If the peripheral circuitry is formed in theretrograde well, the well may have a different dopant profile in theperipheral region than in the array region. The highly concentratedregion at the bottom of the retrograde well reflects signal carriersback to the photosensor so that they are not lost to the substrate. Alsoprovided are methods for forming a pixel sensor cell in the retrogradewell of the present invention.

[0026] The present invention also relates to a pixel sensor cell formedin a retrograde well in a semiconductor substrate together with imagerperiphery formed in an adjacent shallow periphery well. The retrogradewell comprises a doped region with a vertically graded dopantconcentration that is lowest at or near the substrate surface, andhighest at the bottom of the well. The retrograde well would have anentire array of pixels formed therein. The shallow periphery well wouldhave peripheral circuitry formed therein. The shallow periphery well hasa different dopant profile than the retrograde well in the array region.The shallow periphery well has a highly concentrated region at thesurface of the substrate which then gradually diminishes into thesubstrate.

[0027] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a representative circuit of a CMOS imager.

[0029]FIG. 2 is a block diagram of a CMOS pixel sensor chip.

[0030]FIG. 3 is a representative timing diagram for the CMOS imager.

[0031]FIG. 4 is a representative pixel layout showing a 2×2 pixellayout.

[0032]FIG. 5 is a cross-sectional view of two pixel sensor cellsaccording to a first structural embodiment of the present invention.

[0033]FIG. 6 is a graph depicting the dopant concentration as a functionof the depth of the retrograde well.

[0034]FIG. 7 is a cross-sectional view of a semiconductor waferundergoing the process of a first process embodiment of the invention.

[0035]FIG. 8 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 7.

[0036]FIG. 9 is a cross-sectional view of a semiconductor waferundergoing the process of a second process embodiment of the invention.

[0037]FIG. 10 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 9.

[0038]FIG. 11 is a cross-sectional view of two pixel sensor cellsaccording to second structural embodiment of the present invention.

[0039]FIG. 12 is a graph depicting the dopant concentration as afunction of the depth of the periphery well.

[0040]FIG. 13 is a cross-sectional view of a semiconductor waferundergoing the process of a third process embodiment of the invention.

[0041]FIG. 14 shows the wafer of FIG. 13 at a processing step subsequentto that shown in FIG. 13.

[0042]FIG. 15 is an illustration of a computer system having a CMOSimager according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0043] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These to embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0044] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions, junctions or materiallayers in or on the base semiconductor structure or foundation. Inaddition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, or gallium arsenide. Forexemplary purposes an imager formed of n-channel devices in a retrogradep-well is illustrated and described, but it should be understood thatthe invention is not limited thereto, and may include other combinationssuch as an imager formed of p-channel devices in a retrograde n-well.

[0045] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

[0046] The structure of pixel cells 14 formed in retrograde wells 20 ofthe first structured embodiment are shown in more detail in FIG. 5. Apixel cell 14 may be formed in a substrate 16 having a retrograde layeror well 20 of a first conductivity type, which for exemplary purposes istreated as p-type. The retrograde well 20 has a vertically graded dopantconcentration that is lowest at or near the substrate surface, andhighest at the bottom of the well, as is shown in FIG. 6. The dopantconcentration at the top of the retrograde well 20 is within the rangeof about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³, and is preferably withinthe range of about 1×10¹⁵ to about 5×10¹⁶ atoms per cm³, and mostpreferably is about 5×10¹⁵ atoms per cm³. At the bottom of theretrograde well 20, the dopant concentration is within the range ofabout 1×10¹⁶ to about 2×10¹⁸ atoms per cm³, and is preferably within therange of about 5×10¹⁶ to about 1×10¹⁸ atoms per cm³, and most preferablyis about 3×10¹⁷ atoms per cm³. A single retrograde well 20 as depictedin FIG. 5, spans all pixels in the array of pixels. At the surface,there may be V_(t), adjusting dopants that may cause the dopantconcentration to also rise immediately adjacent to the surface to setthe transistor V_(t)s.

[0047] A second retrograde well (not shown) may be formed in thesubstrate 16, and may have peripheral circuitry, such as, e.g., logiccircuitry, formed therein. This second well may be doped similarly ordifferently from the first retrograde well 20, for example, the firstretrograde well 20 may be doped to a first dopant level such as about3×10¹⁷ atoms per cm³ at the bottom of the well and the second well maybe doped to a second dopant level such as 5×10¹⁶ at the bottom of thewell. At the surface in this second retrograde well, there mayadditionally be implants to control the V_(t)s of the transistors inthis second well.

[0048] The pixel cell 14 includes: a photogate 24, a transfer gate 28for transfer transistor 29, and a reset transistor gate 32 for the resettransistor 31. In addition, the photosensitive element in the pixel cell14 is shown to be a photogate 24, but other photosensitive elements suchas a photodiode or a photoconductor could be used. The source followertransistor and the row select transistor are shown schematically in FIG.5. The transfer gate 28 and the reset gate 32 include a gate oxide layer106 on the retrograde well 20, and a conductive layer 108 of dopedpolysilicon, tungsten, or other suitable material over the gate oxidelayer 106. An insulating cap layer 110 of, for example, silicon dioxide,silicon nitride, or ONO (oxide-nitride-oxide), may be formed if desired;also a more conductive layer such as a silicide layer (not shown) may beused between the conductive layer 108 and the cap 110 of the transfergate stack 28, source follower gate, row select gate, and reset gatestack 32, if desired. Insulating sidewalls 112 are also formed on thesides of the gate stacks 28, 32. These sidewalls may be formed of, forexample, silicon dioxide or silicon nitride or ONO. The transfer gate 28is not required but may advantageously be included. The photogate 24 isa semitransparent conductor and is shown as an overlapping gate. Asecond gate oxide 105 is provided over the retrograde well and under thephotogate.

[0049] Underlying the photogate 24 and gate oxide layer 105 is a dopedregion 26 called the photosite, where photogenerated charges are stored.In between the reset transistor gate 32 and the transfer gate 28 is adoped region 30 that is the source for the reset transistor 31, and onthe other side of the reset transistor gate 32 is a doped region 34 thatacts as a drain for the reset transistor 31. The doped regions 26, 30,34 are doped to a second conductivity type, which for exemplary purposesis treated as n-type. The second doped region 30 is a floating diffusionregion, sometimes also referred to as a floating diffusion node, and itserves as the source for the reset transistor 31. The third doped region34 is the drain of the reset transistor 31, and is also connected tovoltage source Vdd.

[0050] As shown in FIG. 5, as light radiation 12 in the form of photonsstrikes the photosite 26, photo-energy is converted to electricalsignals, i.e., carriers 120, which are stored in the photosite 26. Theabsorption of light creates electron-hole pairs. For the case of ann-doped photosite in a p-well, it is the electrons that are stored. Forthe case of a p-doped photosite in an n-well, it is the holes that arestored. In the exemplary pixel cell 14 having n-channel devices formedin a p-type retrograde well 20, the carriers 120 stored in the photosite26 are electrons. The retrograde well 20 acts to reduce carrier loss tothe substrate 16 by forming a concentration gradient that modifies theband diagram and serves to reflect electrons back towards the photosite26, thereby increasing quantum efficiency of the pixel 14.

[0051] The retrograde well 20 is manufactured through a process in afirst process embodiment of the invention described as follows, andillustrated by FIGS. 7 and 8. Referring now to FIG. 7, a substrate 16,which may be any of the types of substrates described above, isprovided. Retrograde well 20 is then formed by suitable means such asblanket ion implantation of the entire wafer. The retrograde well 20 mayalso be implanted at a later stage of the process such as after fieldoxide formation. The implant may be patterned so that the array well andthe periphery logic well could have different doping profiles.

[0052] Ion implantation is performed by placing the substrate 16 in anion implanter, and implanting appropriate dopant ions into the substrate16 at an energy of 100 keV to 5 MeV to form retrograde wells 20 having adopant concentration that is lowest at or near the surface, and highestat the bottom of the well. The dopant concentration at the top of theretrograde well 20 is within the range of about 5×10¹⁴ to about 1×10¹⁷atoms per cm³, and is preferably within the range of about 1×10¹⁵ toabout 5×10¹⁶ atoms per cm³, and most preferably is about 5×10¹⁵ atomsper cm³. At the bottom of the retrograde well 20, the dopantconcentration is within the range of about 1×10¹⁶ to about 2×10¹⁸ atomsper cm³, and is preferably within the range of about 5×10¹⁶ to about1×10¹⁸ atoms per cm³, and most preferably is about 3×10¹⁷ atoms per cm³.If the retrograde well is to be a p-type well, a p-type dopant, such asboron, is implanted, and if the well 20 is to be an n-type well, ann-type dopant, such as arsenic, antimony, or phosphorous is implanted.The resultant structure is shown in FIG. 8. Multiple high energyimplants may be used to tailor the profile of the retrograde well 20.Additionally, there may be V_(t) adjusting implants near the surface toset the V_(t)s of the transistors in the well. For simplicity, FIG. 6does not show any V_(t) adjusting implants near the surface that couldcause the dopant concentration immediately adjacent to the surface toelevate.

[0053] Referring now to FIGS. 9 and 10, which illustrate a secondprocess embodiment of the invention, field oxide regions 114 may beformed around the pixel cell 14 prior to the formation of the retrogradewell 20. The field oxide regions are formed by any known technique suchas thermal oxidation of the underlying silicon in a LOCOS process or byetching trenches and filling them with oxide in an STI process.Following field oxide 114 formation, the retrograde wells 20 may then beformed by blanket implantation as shown in FIG. 10 or by maskedimplantation (not shown).

[0054] Subsequent to formation of the retrograde well 20, by either ofthe processes described above, the devices of the pixel sensor cell 14,including the photogate 24, the transfer gate 28, reset transistor 31,the source follower 36 and the row select transistor 38, all shown inFIG. 5, are formed by well-known methods. Doped regions 26, 30, and 34are formed in the retrograde well 20, and are doped to a secondconductivity type, which for exemplary purposes will be considered to ben-type. The doping level of the doped regions 26, 30, 34 may vary butshould be higher than the doping level at the top of the retrograde well20, and greater than 5×10¹⁶ atoms per cm³. If desired, multiple masksand resists may be used to dope these regions to different levels. Dopedregion 26 may be variably doped, such as either n+ or n− for ann-channel device. Doped region 34 should be strongly doped, i.e., for ann-channel device, the doped region 34 will be doped as n+. Doped region30 is typically strongly doped (n+), and would not be lightly doped (n−)unless a buried contact is also used.

[0055] The pixel sensor cell 14 is essentially complete at this stage,and conventional processing methods may be used to form contacts andwiring to connect gate lines and other connections in the pixel cell 14.For example, the entire surface may then be covered with a passivationlayer of, e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMPplanarized and etched to provide contact holes, which are thenmetallized to provide contacts to the photogate, reset gate, andtransfer gate. Conventional multiple layers of conductors and insulatorsmay also be used to interconnect the structures in the manner shown inFIG. 1.

[0056] Reference is now made to FIG. 11. The structure of pixel cells314 formed in retrograde wells 320 and logic circuitry 360 formed inperiphery wells 350 of a second structural embodiment are shown in moredetail in FIG. 11. A pixel cell 314 may be formed in a substrate 316having a retrograde layer or well 320 of a first conductivity type,which for exemplary purposes is treated as p-type. The retrograde well320 has a vertically graded dopant concentration that is lowest at ornear the substrate surface, and highest at the bottom of the well, as isshown in FIG. 6. The dopant concentration at the top of the retrogradewell 320 is within the range of about 5×10¹⁴ to about 1×10¹⁷ atoms percm³, and is preferably within the range of about 1×10¹⁵ to about 5×10¹⁶atoms per cm³, and most preferably is about 5×10¹⁵ atoms per cm³. At thebottom of the retrograde well 320, the dopant concentration is withinthe range of about 1×10¹⁶ to about 2×10¹⁸ atoms per cm³, and ispreferably within the range of about 5×10¹⁶ to about 1×10¹⁸ atoms percm³, and most preferably is about 3×10¹⁷ atoms per cm³.

[0057] A periphery well 350 is formed in the substrate 316, and may haveperipheral circuitry, such as, e.g., logic circuitry, formed therein.The periphery well 350 is doped differently from the retrograde well320. For example, the periphery well may be doped to a first dopantlevel from about 1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the top of saidretrograde well, preferably from about 5×10¹⁶ to about 1×10¹⁸, mostpreferably from about 3×10¹⁷ atoms per cm³. A representative dopingconcentration for the periphery well 350 is shown in FIG. 12. Forsimplicity, FIG. 12 does not show any V_(t) adjusting implants near thesurface that could cause the dopant concentration immediately adjacentto the surface to elevate. As can be seen by comparing FIGS. 6 and 12,while the doping concentration of the retrograde well increases withdepth to a certain point, the doping concentration of the periphery welldecreases with depth. Moreover, as illustrated in FIG. 11, theretrograde well extends deeper into the substrate than does theperiphery well. The retrograde well 320 and periphery well 350 are shownin FIG. 11 as being separated by field oxide regions 310.

[0058] The pixel cell 314 includes: a photogate 324, a transfertransistor 328, and a reset transistor 332. In addition, thephotosensitive element in the pixel cell 314 is shown to be a photogate324, but other photosensitive elements such as a photodiode or aphotoconductor could be used. The source follower transistor and the rowselect transistor are not shown but are schematically arranged the sameas transistors 36 and 38 shown in FIG. 5. The transfer transistor 328and the reset transistor 332 include a gate oxide layer 327 and aconductive layer 329 of doped polysilicon, tungsten, or other suitablematerial over the gate oxide layer as described above with reference toFIG. 5. An insulating cap layer 331 of, for example, silicon dioxide,silicon nitride, or ONO (oxide-nitride-oxide), may be formed if desired;also a more conductive layer such as a silicide layer (not shown) may beused between the conductive layer and the cap of the transfer transistor328 and reset transistor 332, if desired. Insulating sidewalls 333 arealso formed on the sides of the transistor gate stacks 328, 332. Thesesidewalls may be formed of, for example, silicon dioxide or siliconnitride or ONO. The transfer transistor is not required but mayadvantageously be included. The photogate 324 is a semitransparentconductor and is shown as an overlapping gate.

[0059] Underlying the photogate 324 is an oxide layer 335 and below thata doped region 326 which acts as the photosite, where photogeneratedcharges are stored. In between the reset transistor 332 and the transfertransistor 328 is a doped region 330 that is the source for the resettransistor 332, and on the other side of the reset transistor gate 332is a doped region 334 that acts as a drain for the reset transistor 332.The doped regions 326, 330, 334 are doped to a second conductivity type,which for exemplary purposes is treated as n-type. The second dopedregion 330 is the floating diffusion region, sometimes also referred toas a floating diffusion node, and it serves as the source for the resettransistor 332. The third doped region 334 is the drain of the resettransistor 332, and is also connected to voltage source Vdd. The line339 is a conductor which connects to a source follower and row selecttransistor in the manner illustrated in FIG. 5.

[0060] The retrograde well 320 acts to reduce carrier loss to thesubstrate 316 by forming a concentration gradient that modifies the banddiagram and serves to reflect electrons back towards the photosite 326,thereby increasing quantum efficiency of the pixel 314.

[0061] The periphery well 350 may include periphery and logic circuitry.The periphery circuit is depicted as readout transistor circuit 360 inFIG. 11, however, it should be understood that readout circuit mayinclude periphery and logic circuitry such as, for example, a signalsample and hold (S/H) circuit and a reset sample and hold circuit. Thesignal sample and hold circuit may include a S/H n-channel field effecttransistor and a signal storage capacitor, and load transistor, as shownin FIG. 1 and described above. The reset sample and hold (S/H) circuitmay include a S/H transistor, a signal storage capacitor, p-channeloutput transistor, p-channel column select transistor, load transistoror any other similar transistor, as shown in FIG. 1 and described above.

[0062] The substrate including retrograde and periphery wells 320, 350is manufactured through a process in a third process embodimentdescribed as follows, and illustrated by FIGS. 13 and 14. Referring nowto FIG. 13, a substrate 316, which may be any of the types of substratesdescribed above, is provided. Retrograde well 320 is then formed bysuitable means such as blanket ion implantation of the entire wafer,with or without masking. FIG. 13 shows a masked ion implantation. Theretrograde well 320 may be implanted at a later stage of the processsuch as after field oxide formation or after implantation of theperiphery well.

[0063] Ion implantation for well 320 is performed by placing thesubstrate 316 in an ion implanter, and implanting appropriate dopantions into the substrate 316 at an energy of 100 keV to 5 MeV to formretrograde wells 320 having a dopant concentration that is lowest at ornear the surface, and highest at the bottom of the well. The dopantconcentration at the top of the retrograde well 320 is within the rangeof about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³, and is preferably withinthe range of about 1×10¹⁵ to about 5×10¹⁶ atoms per cm³, and mostpreferably is about 5×10¹⁵ atoms per cm³. At the bottom of theretrograde well 20, the dopant concentration is within the range ofabout 1×10¹⁶ to about 2×10¹⁸ atoms per cm³, and is preferably within therange of about 5×10¹⁶ to about 1×10¹⁸ atoms per cm³, and most preferablyis about 3×10¹⁷ atoms per cm³. If the retrograde well is to be a p-typewell, a p-type dopant, such as boron, is implanted, and if the well 320is to be an n-type well, an n-type dopant, such as arsenic, antimony, orphosphorous is implanted.

[0064] Reference is now made to FIG. 14. Periphery well 350 is thenformed by suitable means such as masked blanket ion implantation of theentire wafer. The periphery well 350 may be implanted at a later stageof the process such as after field oxide formation or before theimplantation of retrograde well 320.

[0065] Ion implantation is performed by placing the substrate 316 in anion implanter, and implanting appropriate dopant ions into the substrate316 at an energy of 100 keV to 5 MeV to form periphery well 350 having adopant concentration that is highest at the surface, and decreasesasymptotically to the bottom of the well. The dopant concentration atthe top of the periphery well 350 is within the range of dopantconcentration is within the range of about 1×10¹⁶ to about 2×10¹⁸ atomsper cm³, and is preferably within the range of about 5×10¹⁶ to about1×10¹⁸ atoms per cm³, and most preferably is about 3×10¹⁷ atoms per cm³.If the periphery well 350 is to be a p-type well, a p-type dopant, suchas boron, is implanted, and if the periphery well 350 is to be an n-typewell, an n-type dopant, such as arsenic, antimony, or phosphorous isimplanted.

[0066] The pixel sensor cell 314 is then subjected to conventionalprocessing methods to form other elements, contacts, wiring to connectgate lines and the like to arrive at the structure generally shown inFIG. 1.

[0067] A typical processor based system which includes a CMOS imagerdevice according to the present invention is illustrated generally at400 in FIG. 15. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision system, vehicle navigation system, videotelephone, surveillance system, auto focus system, star tracker system,motion detection system, image stabilization system and data compressionsystem for high-definition television, all of which can utilize thepresent invention.

[0068] A processor system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 444, e.g., amicroprocessor, that communicates with an input/output (I/O) device 446over a bus 452. The CMOS imager 442 also communicates with the systemover bus 452. The computer system 400 also includes random access memory(RAM) 448, and, in the case of a computer system may include peripheraldevices such as a floppy disk drive 454 and a compact disk (CD) ROMdrive 456 which also communicate with CPU 444 over the bus 452. CMOSimager 442 is preferably constructed as an integrated circuit whichincludes pixels containing a photosensor such as a photogate orphotodiode formed in a retrograde well, as previously described withrespect to FIGS. 5 through 14. The CMOS imager 442 may be combined witha processor, such as a CPU, digital signal processor or microprocessor,with or without memory storage in a single integrated circuit, or may beon a different chip than the processor.

[0069] As can be seen by the embodiments described herein, the presentinvention encompasses a pixel sensor cell formed in a retrograde well.The pixel sensor cell has improved quantum efficiency and an improvedsignal-to-noise ratio due to the presence of a doping gradient inducedelectric field created in the bottom eof the retrograde well whichreflects signal carriers back to the photosensitive node. By reflectingphotogenerated carriers back to the storage node the retrograde p-wellalso reduces the number of carriers diffusing to adjacent pixels and soalso reduces cross talk.

[0070] It should again be noted that although the invention has beendescribed with specific reference to CMOS imaging circuits having aphotogate and a floating diffusion region, the invention has broaderapplicability and may be used in any CMOS imaging apparatus. Similarly,the process described above is but one method of many that could beused. The above description and drawings illustrate preferredembodiments which achieve the objects, features and advantages of thepresent invention. It is not intended that the present invention belimited to the illustrated embodiments. Any modification of the presentinvention which comes within the spirit and scope of the followingclaims should be considered part of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A pixel sensor cell for an imaging device, saidpixel sensor cell comprising: a retrograde well of a first conductivitytype formed in a substrate; a photosensitive region formed in saidretrograde well; a floating diffusion region of a second conductivitytype formed in said retrograde well for receiving charges transferredfrom said photosensitive region; a periphery well of one of said firstor second conductivity type formed in said substrate in proximity tosaid retrograde well; and peripheral devices formed in said peripherywell.
 2. A pixel sensor cell according to claim 1, wherein the firstconductivity type is p-type and the second conductivity type is n-type.3. The pixel sensor cell according to claim 2, wherein said retrogradewell is doped with boron.
 4. The pixel sensor cell according to claim 2,wherein said periphery well has said second conductivity and is dopedwith a dopant selected from the group consisting of arsenic, antimony,and phosphorous.
 5. The pixel sensor cell according to claim 1, whereinthe first conductivity type is n-type and the second conductivity typeis p-type.
 6. The pixel sensor cell according to claim 5, wherein saidretrograde well is doped with a dopant selected from the groupconsisting of arsenic, antimony, and phosphorous.
 7. The pixel sensorcell according to claim 5, wherein said periphery well has said secondconductivity and is doped with boron.
 8. The pixel sensor according toclaim 1, wherein the doping concentration of said retrograde wellincreases from the top toward the bottom of said retrograde well for atleast an upper portion of said retrograde well.
 9. The pixel sensoraccording to claim 1, wherein the doping concentration of said peripherywell decreases from the top toward the bottom of said periphery well.10. The pixel sensor according to claim 1, wherein said retrograde wellis deeper than said periphery well.
 11. The pixel sensor cell accordingto claim 8, wherein said retrograde well has a dopant concentrationwithin the range of about 1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at thebottom of said retrograde well.
 12. The pixel sensor cell according toclaim 8, wherein said retrograde well has a dopant concentration withinthe range of about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³ at the top ofsaid retrograde well.
 13. The pixel sensor cell according to claim 11,wherein said retrograde well has a dopant concentration within the rangeof about 5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of saidretrograde well.
 14. The pixel sensor cell according to claim 12,wherein said retrograde well has a dopant concentration within the rangeof about 1×10¹⁵ to about 5×10¹⁶ atoms per cm³ at the top of saidretrograde well.
 15. The pixel sensor cell according to claim 13,wherein said retrograde well has a dopant concentration of about 3×10¹⁷atoms per cm³ at the bottom of said retrograde well.
 16. The pixelsensor cell according to claim 14, wherein said retrograde well has adopant concentration of about 5×10¹⁵ atoms per cm³ at the top of saidretrograde well.
 17. The pixel sensor cell according to claim 9, whereinsaid periphery well has a dopant concentration within the range of about1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the top of said periphery well.18. The pixel sensor cell according to claim 17, wherein said peripherywell has a dopant concentration within the range of about 5×10¹⁶ toabout 1×10¹⁸ atoms per cm³ at the top of said periphery well.
 19. Thepixel sensor cell according to claim 18, wherein said periphery well hasa dopant concentration of about 3×10¹⁷ atoms per cm³ at the top of saidperiphery well.
 20. The pixel sensor cell according to claim 9, whereinsaid periphery well has a dopant concentration greater than or equal to1×10¹⁶ atoms per cm³ at the bottom of said periphery well.
 21. The pixelsensor cell according to claim 20, wherein said retrograde well has adopant concentration of about 5×10¹⁵ atoms per cm³ at the bottom of saidperiphery well.
 22. The pixel sensor cell according to claim 1, furthercomprising a photosensor formed on said photosensitive region forcontrolling the collection of charges in said photosensitive region. 23.The pixel sensor cell according to claim 22, wherein said photosensor isa photodiode sensor.
 24. The pixel sensor cell according to claim 22,wherein said photosensor is a photogate sensor.
 25. The pixel sensorcell according to claim 22, wherein said photosensor is a photoconductorsensor.
 26. The pixel sensor cell according to claim 1, furthercomprising a transfer gate formed on said retrograde well between saidphotosensitive region and said floating diffusion region.
 27. The pixelsensor cell according to claim 1, further comprising a reset transistorformed in said retrograde well for periodically resetting a charge levelof said floating diffusion region, said floating diffusion region beingthe source of said reset transistor.
 28. A pixel sensor cell for animaging device, said pixel sensor cell comprising: a retrograde well ofa first conductivity type formed in a substrate; a photosensor formed insaid retrograde well; a reset transistor having a gate stack formed insaid retrograde well; a floating diffusion region of a secondconductivity type formed in said retrograde well between saidphotosensor and reset transistor for receiving charges from saidphotosensor, said reset transistor operating to periodically reset acharge level of said floating diffusion region; a periphery well of oneof said first and second conductivity type formed in said substrateadjacent said retrograde well; and an output transistor having a gateelectrically connected to said floating diffusion region, wherein saidoutput transistor is formed in said periphery well.
 29. The pixel sensorcell according to claim 28, wherein said photosensor further comprises adoped region of a second conductivity type located in said retrogradewell.
 30. The pixel sensor cell according to claim 28, wherein saidphotosensor is a photodiode sensor.
 31. The pixel sensor cell accordingto claim 28, wherein said photosensor is a photoconductor sensor. 32.The pixel sensor cell according to claim 28, further comprising atransfer gate located between said photosensor and said floatingdiffusion region.
 33. The pixel sensor cell according to claim 32,wherein said photosensor is a photogate sensor.
 34. The pixel sensorcell according to claim 28, wherein the first conductivity type isp-type and the second conductivity type is n-type.
 35. The pixel sensorcell according to claim 34, wherein said retrograde well is doped withboron.
 36. The pixel sensor according to claim 34, wherein saidperiphery well ha said second conductivity and is doped with a dopantselected from the group consisting of arsenic, antimony, andphosphorous.
 37. The pixel sensor cell according to claim 28, whereinthe first conductivity type is n-type and the second conductivity typeis p-type.
 38. The pixel sensor cell according to claim 37, wherein saidretrograde well is doped with a dopant selected from the groupconsisting of arsenic, antimony, and phosphorous.
 39. The pixel sensorcell according to claim 37, wherein said periphery well has said secondconductivity and is doped with boron.
 40. The pixel sensor according toclaim 28, wherein the doping concentration of said retrograde wellincreases from the top toward the bottom of said retrograde well for atleast an upper portion of said retrograde well.
 41. The pixel sensoraccording to claim 28, wherein the doping concentration of saidperiphery well decreases from the top toward the bottom of saidperiphery well.
 42. The pixel sensor according to claim 28, wherein saidretrograde well is deeper than said periphery well.
 43. The pixel sensorcell according to claim 40, wherein said retrograde well has a dopantconcentration within the range of about 1×10¹⁶ to about 2×10¹⁸ atoms percm³ at the bottom of said retrograde well.
 44. The pixel sensor cellaccording to claim 40, wherein said retrograde well has a dopantconcentration within the range of about 5×10¹⁴ to about 1×10¹⁷ atoms percm³ at the top of said retrograde well.
 45. The pixel sensor cellaccording to claim 43, wherein said retrograde well has a dopantconcentration within the range of about 5×10¹⁶ to about 1×10¹⁸ atoms percm³ at the bottom of said retrograde well.
 46. The pixel sensor cellaccording to claim 44, wherein said retrograde well has a dopantconcentration within the range of about 1×10¹⁵ to about 5×10¹⁶ atoms percm³ at the top of said retrograde well.
 47. The pixel sensor cellaccording to claim 45, wherein said retrograde well has a dopantconcentration of about 3×10¹⁷ atoms per cm³ at the bottom of saidretrograde well.
 48. The pixel sensor cell according to claim 46,wherein said retrograde well has a dopant concentration of about 5×10¹⁵atoms per cm³ at the top of said retrograde well.
 49. The pixel sensorcell according to claim 41, wherein said periphery well has a dopantconcentration within the range of about 1×10¹⁶ to about 2×10¹⁸ atoms percm³ at the top of said periphery well.
 50. The pixel sensor cellaccording to claim 49, wherein said periphery well has a dopantconcentration within the range of about 5×10¹⁶ to about 1×10¹⁸ atoms percm³ at the top of said periphery well.
 51. The pixel sensor cellaccording to claim 50, wherein said periphery well has a dopantconcentration of about 3×10¹⁷ atoms per cm³ at the top of said peripherywell.
 52. The pixel sensor according to claim 41, wherein said peripherywell has a dopant concentration of greater than or equal to 1×10¹⁶ atomsper cm³ at the bottom of said periphery well.
 53. The pixel sensor cellaccording to claim 52, wherein said periphery well has a dopantconcentration of about 5×10¹⁵ atoms per cm³ at the bottom of saidperiphery well.
 54. A CMOS imager comprising: a substrate having atleast one retrograde well of a first conductivity type; an array ofpixel sensor cells formed in said at least one retrograde well, whereineach pixel sensor cell has a photosensor; at least one periphery well ofsaid first or a second conductivity type formed in a substrate; and acircuit formed in said periphery well, said circuit being electricallyconnected to receive and process output signals from said array.
 55. TheCMOS imager according to claim 54, wherein said at least one retrogradewell comprises one retrograde well.
 56. The CMOS imager according toclaim 54, wherein said at least one periphery well includes oneperiphery well.
 57. The CMOS imager according to claim 54, wherein thefirst conductivity type is p-type and the second conductivity type isn-type.
 58. The CMOS imager according to claim 54, wherein said at leastone retrograde well is doped with boron.
 59. The CMOS imager accordingto claim 54, wherein said at least one periphery well has said secondconductivity and is doped with a dopant selected from the groupconsisting of arsenic, antimony, and phosphorous.
 60. The CMOS imageraccording to claim 54, wherein the first conductivity type is n-type andthe second conductivity type is p-type.
 61. The CMOS imager according toclaim 60, wherein said at least one retrograde well is doped with adopant selected from the group consisting of arsenic, antimony, andphosphorous.
 62. The CMOS imager according to claim 60, wherein said atleast one periphery well has said second conductivity and is doped withboron.
 63. The CMOS imager according to claim 54, wherein each pixelsensor cell further comprises a transfer gate located between a saidphotosensor and a floating diffusion region.
 64. The CMOS imageraccording to claim 63, wherein the photosensors are photogate sensors.65. The pixel sensor according to claim 54, wherein the dopingconcentration of said retrograde well increases from the top toward thebottom of said retrograde well for at least an upper portion of saidretrograde well.
 66. The pixel sensor according to claim 54, wherein thedoping concentration of said periphery well decreases from the toptoward the bottom of said periphery well.
 67. The pixel sensor accordingto claim 54, wherein said retrograde well is deeper than said peripherywell.
 68. The CMOS imager according to claim 65, wherein said retrogradewell has a dopant concentration within the range of about 1×10¹⁶ toabout 2×10¹⁸ atoms per cm³ at the bottom of said retrograde well. 69.The CMOS imager according to claim 65, wherein said retrograde well hasa dopant concentration within the range of about 5×10¹⁴ to about 1×10¹⁷atoms per cm³ at the top of said retrograde well.
 70. The CMOS imageraccording to claim 68, wherein said retrograde well has a dopantconcentration within the range of about 5×10¹⁶ to about 1×10¹⁸ atoms percm³ at the bottom of said retrograde well.
 71. The CMOS imager accordingto claim 69, wherein said retrograde well has a dopant concentrationwithin the range of about 1×10¹⁵ to about 5×10¹⁶ atoms per cm³ at thetop of said retrograde well.
 72. The CMOS imager according to claim 70,wherein said retrograde well has a dopant concentration of about 3×10¹⁷atoms per cm³ at the bottom of said retrograde well.
 73. The CMOS imageraccording to claim 71, wherein said retrograde well has a dopantconcentration of about 5×10¹⁵ atoms per cm³ at the top of saidretrograde well.
 74. The CMOS imager according to claim 66, wherein saidperiphery well has a dopant concentration within the range of about1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the top of said retrograde well.75. The CMOS imager according to claim 74, wherein said periphery wellhas a dopant concentration within the range of about 5×10¹⁶ to about1×10¹⁸ atoms per cm³ at the top of said retrograde well.
 76. The CMOSimager according to claim 75) wherein said periphery well has a dopantconcentration of about 3×10¹⁷ atoms per cm³ at the top of said peripherywell.
 77. The CMOS imager according to claim 66, wherein said peripherywell has a dopant concentration greater than or equal to 1×10¹⁶ atomsper cm³ at the bottom of said periphery well.
 78. The CMOS imageraccording to claim 77, wherein said periphery well has a dopantconcentration of about 5×10¹⁵ atoms per cm³ at the bottom of saidperiphery well.
 79. The CMOS imager according to claim 54, wherein thephotosensors are photodiode sensors.
 80. The CMOS imager according toclaim 54, wherein the photosensors are photoconductor sensors.
 81. TheCMOS imager according to claim 54, wherein the photosensors arephotogate sensors.
 82. A method of forming a photosensor for an imagingdevice, said method comprising: forming a retrograde well of a firstconductivity type in a substrate; forming a periphery well of said firstor a second conductivity in the substrate; forming a photosensor withinthe retrograde well; and forming output circuitry within the peripherywell.
 83. A method as in claim 82, wherein the periphery well is of saidsecond conductivity type.
 84. The method according to claim 82, whereinforming said retrograde includes an ion implantation step.
 85. Themethod according to claim 82, wherein forming a periphery well includesan ion implantation step.
 86. The method of claim 82, wherein saidretrograde well is formed such that it increases from the top toward thebottom of said retrograde well for at least an upper portion of saidretrograde well.
 87. The method of claim 82, wherein said periphery wellis formed such that it decreases from the top toward the bottom of saidperiphery well.
 88. The method of claim 82, wherein said retrograde wellis deeper than said periphery well.
 89. The method according to claim82, wherein the first conductivity type is p-type and said secondconductivity is n-type
 90. The method according to claim 82, whereinsaid periphery well is formed as said first conductivity type.
 91. Themethod according to claim 89, wherein the retrograde well is doped withboron.
 92. The method according to claim 90, wherein the periphery wellis doped with a dopant selected from the group consisting of arsenic,antimony, and phosphorous.
 93. The method according to claim 82, whereinthe first conductivity type is n-type and said second conductivity typeis p-type.
 94. The method according to claim 93, wherein the retrogradewell is doped with a dopant selected from the group consisting ofarsenic, antimony, and phosphorous.
 95. The method according to claim93, wherein the periphery well is doped with boron.
 96. The methodaccording to claim 86, wherein said formed retrograde well has a dopantconcentration within the range of about 1×10¹⁶ to about 2×10¹⁸ atoms percm³ at the bottom of said retrograde well.
 97. The method according toclaim 86, wherein said formed retrograde well has a dopant concentrationwithin the range of about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³ at thetop of said retrograde well.
 98. The method according to claim 96,wherein said formed retrograde well has a dopant concentration withinthe range of about 5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom ofsaid retrograde well.
 99. The method according to claim 97, wherein saidformed retrograde well has a dopant concentration within the range ofabout 1×10¹⁵ to about 5×10¹⁶ atoms per cm³ at the top of said retrogradewell.
 100. The method according to claim 98, wherein said formedretrograde well has a dopant concentration of about 3×10¹⁷ atoms per cm³at the bottom of said retrograde well.
 101. The method according toclaim 99, wherein said formed retrograde well has a dopant concentrationof about 5×10¹⁵ atoms per cm³ at the top of said retrograde well. 102.The method according to claim 87, wherein said formed periphery well hasa dopant concentration within the range of about 1×10¹⁶ to about 2×10¹⁸atoms per cm³ at the top of said periphery well.
 103. The methodaccording to claim 102, wherein said formed periphery well has a dopantconcentration within the range of about 5×10¹⁶ to about 1×10¹⁸ atoms percm³ at the top of said retrograde well.
 104. The method according toclaim 103, wherein said formed periphery well has a dopant concentrationof about 3×10¹⁷ atoms per cm³ at the top of said retrograde well. 105.The method according to claim 87, wherein said formed periphery well hasa dopant concentration greater than or equal to 1×10¹⁶ atoms per cm³ atthe bottom of said periphery well.
 106. The method according to claim105, wherein said periphery well has a dopant concentration of about5×10¹⁵ atoms per cm³ at the bottom of said periphery well.
 107. Themethod according to claim 82, wherein the photosensor forming step is aphotodiode sensor forming step.
 108. The method according to claim 82,wherein the photosensor forming step is a photoconductor forming step.109. The method according to claim 82, wherein the photosensor formingstep is a photogate forming step.
 110. The method according to 82,further comprising forming a diffusion node in said retrograde well andforming a transfer gate in said retrograde well between said photosensorand diffusion node.
 111. A method of forming a pixel sensor cell for animaging device, said method comprising: forming a retrograde well of afirst conductivity type in a substrate; forming a periphery well of afirst conductivity type in said substrate adjacent said retrograde well;forming a photosensitive region in the retrograde well; forming aphotosensor on an upper surface of the photosensitive region forcontrolling the collection of charge therein; forming a floatingdiffusion region of a second conductivity type in the retrograde wellfor receiving charges transferred from said photosensitive region; andforming output circuitry on an upper surface of said periphery well.112. The method of claim 111, wherein said retrograde well is formedsuch that it increases from the top toward the bottom of said retrogradewell for at least an upper portion of said retrograde well.
 113. Themethod of claim 111, wherein said periphery well is formed such that itdecreases from the top toward the bottom of said periphery well. 114.The method of claim 111, wherein said retrograde well is deeper thansaid periphery well.
 115. The method according to claim 111, wherein thefirst conductivity type is p-type, and the second conductivity type isn-type.
 116. The method according to claim 115, wherein the retrogradewell is doped with boron.
 117. The method according to claim 115,wherein the periphery well is doped with boron.
 118. The methodaccording to claim 111, wherein the first conductivity type is n-type,and the second conductivity type is p-type.
 119. The method according toclaim 118, wherein the retrograde well is doped with a dopant selectedfrom the group consisting of arsenic, antimony, and phosphorous. 120.The method according to claim 118, wherein the periphery well is dopedwith a dopant selected from the group consisting of arsenic, antimony,and phosphorous.
 121. The method according to claim 112, wherein saidformed retrograde well has a dopant concentration within the range ofabout 1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the bottom of saidretrograde well.
 122. The method according to claim 112, wherein saidformed retrograde well has a dopant concentration within the range ofabout 5×10¹⁴ to about 1×10¹⁷ atoms per cm³ at the top of said retrogradewell.
 123. The method according to claim 121, wherein said formedretrograde well has a dopant concentration within the range of about1×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of said retrogradewell.
 124. The method according to claim 122, wherein said formedretrograde well has a dopant concentration within the range of about1×10¹⁵ to about 5×10¹⁶ atoms per cm³ at the top of said retrograde well.125. The method according to claim 123, wherein said formed retrogradewell has a dopant concentration of about 3×10¹⁷ atoms per cm³ at the bottom of said retrograde well.
 126. The method according to claim 124,wherein said formed retrograde well has a dopant concentration withinthe range of about 5×10¹⁵ atoms per cm³ at the top of said retrogradewell.
 127. The method according to claim 113, wherein said formedperiphery well has a dopant concentration within the range of about1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the top of said periphery well.128. The method according to claim 127, wherein said formed peripherywell has a dopant concentration within the range of about 5×10¹⁶ toabout 1×10¹⁸ atoms per cm³ at the top of said periphery well.
 129. Themethod according to claim 128, wherein said formed periphery well has adopant concentration of about 3×10¹⁷ atoms per cm³ at the top of saidperiphery well.
 130. The method according to claim 113, wherein saidformed periphery well has a dopant concentration greater than or equalto 1×10¹⁶ atoms per cm³ at the bottom of said periphery well.
 131. Themethod according to claim 130, wherein said formed periphery well has adopant concentration of about 5×10¹⁵ atoms per cm³ at the bottom of saidperiphery well.
 132. The method according to claim 111, wherein thephotosensor is a photodiode sensor.
 133. The method according to claim111, wherein the photosensor is a photoconductor sensor.
 134. The methodaccording to claim 111, wherein the photosensor is a photogate sensor.135. The method according to claim 111, further comprising forming atransfer gate on the retrograde well between the photosensor and thefloating diffusion region.